Technical Writers for Microprocessors, Semiconductors, and Software

Networking and Communication

The Delay-Tolerant Networks Tutorial, written for the Internet Research Task Force (IRTF), describes the architecture of a mobile Internet protocol for Earth and outer-space.

Altera's Interlaken Megacore Function Users Guide describes their serial communication protocol for chip-to-chip packet transfers.

IBM's PowerEN PCIe Card User Manual describes a card that uses an IBM PowerEN processor to monitor high-volume packet traffic in edge-of-network routers.

The Multicore Association's Multicore Communications API (MCAPI) Specification supports interaction between multiple processing cores, as does their Multicore Resource API (MRAPI) Specification.

NeoMagic's LinkUp L7205 Internet System Processor (DSP Enhanced) Databook describes the instructions and microarchitecture of their Arm-based, DSP-enhanced Internet processor.

Orbcomm's Machine-to-Machine (M2M) Provisioning Portal Developer API Specification defines their web services description language (WSDL) interface for satellite and cellular-network tracking.

AMD's K9 Message Engine Architecture, describes a hardware accelerator design for high-speed message exchange.

Myricom's Datagram Bypass Layer (DBL) User Guide describes their software for accelerating enterprise applications that depend on user datagram protocol (UDP) latency.

The Synopsys Systems-on-Chip for High-Speed Communication Systems white paper describes design issues and solutions for ASIC-based SoCs used in broadband communications.

Analog Devices' AD6489 Integrated Broadband Communications Processor Programmers Reference Manual describes implementation of OSI Layer 3+ services.

Programming and Application Programming Interfaces (APIs)

Sony's PlayStation 4 Performance Optimization Guide describes best programming techniques for the graphics processing unit (GPU) used in this game platform.

IBM's PowerEN PCIe Card User Manual describes this single-board computer’s API function calls for parallel edge-of-network applications.

Multicore Association's Multicore Resource API (MRAPI) Specification defines an API for management of shared resources in multicore embedded systems. See also the Multicore Communications API (MCAPI) Specification.

AMD's x86-64 Architecture Programmers Manual describes and illustrates the use of their 64-bit x86 application- and system-programming instruction set.

Plurality's HyperCore Software Developer's Handbook describes a fine-grained, task-oriented programming model for parallel applications managed by a hardware synchronizer and scheduler.

The Tizen Linux Mobile (LiMo) API Document Guidelines describes the API functions for a hardware-independent, generic application platform for Linux-based mobile devices.

The Sony, Toshiba, IBM (STI) Cell Broadband Engine Programming Handbook is a 900-page book describing programming for the nine heterogeneous cores used in the Sony PlayStation 3 game platform.

NVIDIA's PortalPlayer Tango Software Developer's Guide describes the API functions for a hardware-specific audio device driver and LCD.

Warthman Associates' Java API for network animation.

ORBCOMM's Machine-to-Machine (M2M) Provisioning Portal Developer API Specification describes their web services description language (WSDL) interface for satellite and cellular-network asset tracking.

The AMD/ATI Compute Abstraction Layer (CAL) Intermediate Language (IL) Reference Manual describes the intermediate instructions used by their GPU compiler.

Analog Devices' AD6489 Integrated Broadband Communications Processor Programmers Reference Manual describes the software implementation of broadband services and physical interfaces.

MicroUnity's BroadMX C/C++ Functions manual describes an instruction-set architecture that includes many vector instructions for graphics, such as convolutions on complex floating-point operands.

IBM's PowerPC Compiler Writer's Guide describes how to write a compiler for microprocessors that run the PowerPC instruction-set architecture.

Cadence Tensilica's Instruction Set Architecture (ISA) Reference Manual describes their instruction set and programming model for configurable embedded processors and intellectual-property (IP) cores.

Cadence Tensilica's Instruction Extension (TIE) Reference Manual describes a software technology for creating new macro instructions using Verilog-like expressions.

The nCUBE 2 Supercomputers Parallel Programming Principles manual describes the basic principles by which high-performance parallel programs can be created for nCube's supercomputers.

Hitachi's (now Renesas') SH-DSP Programming Manual describes the instruction-set architecture for their SH-DSP processors.

IBM's Metaphor Database Design Reference Manual describes how to design and program enterprise SQL relational databases.

Graphics

Sony's PlayStation 4 Performance Optimization Guide describes the best programming techniques for the graphics processing unit (GPU) used in this game platform.

The Sony, Toshiba, IBM (STI) Cell Broadband Engine Programming Handbook describes programming for this Cell Processor chip, which is used in the Sony PlayStation 3 game platform.

The AMD/ATI R600-Family Instructions Set Architecture Manual describes the instructions for high-performance graphics processing units (GPUs).

The AMD/ATI Compute Abstraction Layer (CAL) Intermediate Language (IL) Reference Manual describes the intermediate instructions used by GPU compilers.

Sony's Guide to Cell/B.E. Programming Documentation for the Sony PlayStation 3, in which a PowerPC core manages eight SIMD cores.

MicroUnity's BroadMX C/C++ Functions manual describes a 128-bit architecture that includes many vector instructions for graphics, such as convolutions on complex floating-point operands.

The MicroDesign Resources (MDR) 3D Technology Report is an architectural research paper about a variety of 3D-graphics chips.

Intel's 830M Chipset Mobile Graphics Controller manual describes an Intel graphics-controller technology for wireless mobile computers.

Fujitsu's SPARClite MB86937 Lumiere RISC Imaging Accelerator User's Manual describes an embedded processor with graphics acceleration implemented as a systems-on-chip (SoC).

Specifications and Standards

We have edited many Mobile Industry Processor Interface (MIPI) Alliance Specifications in support of cell phones and other mobile devices. A few examples are shown below.

The Mobile Industry Processor Interface (MIPI) Alliance's Specification for Unified Protocol (UniPro) v2.0 defines a layered protocol for interconnecting devices and components within mobile systems.

The Mobile Industry Processor Interface (MIPI) Alliance's Camera Serial Interface 3 (CSI-3) specifies a serial interface for integration of camera subsystems and bridge devices with a host processor.

The Mobile Industry Processor Interface (MIPI) Alliance's Specification for Battery Interface (BIF) specifies a serial interface for integration of camera subsystems and bridge devices with a host processor.

The MIPI Alliance's Specification for Unified Protocol (UniPro) SDL State Machines defines Specification and Description Language (SDL) state machines for cell phones and mobile devices.

The Mobile Industry Processor Interface (MIPI) Alliance's Specification for Device Descriptor Block (DDB) specifies services that transfer descriptor and configuration data between devices on a MIPI Interconnect.

The MIPI Alliance's Specification for Serial Low-power Inter-chip Media Bus (SLIMbus) defines a two-wire multi-drop interface for digital audio and control devices.

The MIPI Alliance's Specification for RF Front-End (RFFE) Control Interface defines a common method for controlling RF front-end devices.

The Mobile Industry Processor Interface (MIPI) Alliance's Specification for NAND Software L2 Interface specifies the API for mobile devices that use embedded NAND and NAND-like devices.

The Near Field Communication (NFC) Forum's Test Cases for Digital Protocol, one of several NFC standards that we edited.

The Tizen Linux Mobile (LiMo) Foundation's Software Architecture Document, one of several Linux-based mobile-device standards that we edited in cooperation with the IEEE-ISTO.

Parallel Processing

Sony's PlayStation 4 Performance Optimization Guide describes the best parallel programming techniques for the graphics processing unit (GPU) used in this game platform.

The AMD/ATI R600-Family Instructions Set Architecture Manual describes the instructions for parallel high-performance graphics processing units (GPUs).

Adapteva's Epiphany Architecture Reference Manual describes the instruction set, pipeline, and Network on Chip (NoC) for their multicore parallel-computing fabric.

Plurality's HyperCore Software Developer's Handbook describes a fine-grained, task-oriented programming model for parallel applications managed by a hardware synchronizer and scheduler.

The Multicore Association's Multicore Resource API (MRAPI) Specification defines an API for management of parallel, shared resources in multicore embedded systems.

AMD's SimNow Simulator 3.0 User Manual describes a software simulator that supports BIOS and OS development and memory-parameter tuning in multicore parallel architectures.

The Sony, Toshiba, IBM (STI) Cell Broadband Engine Programming Handbook describes parallel programming for this Cell Processor chip, which is used in the Sony PlayStation 3 game platform.

This excerpt from the nCUBE 2 Supercomputers Parallel Programming Principles describes how to partition databases running on nCube parallel-processing supercomputers.

Multicore Processors

Arm's Architecture Reference Manual describes the ARMv8 multicore microprocessor architecture.

Arm's Architecture Reference Manual Supplement describes the Memory System Resource Partitioning and Monitoring (MPAM) extension for the Arm microprocessor architecture.

AppliedMicro's X-Gene 3 64-bit ARM Server SoC User's Manual describes an Arm multicore SoC for data-center applications. We also did their:
X-Gene 2 User Manual and
X-Gene 1 User Manual

Adapteva's Epiphany Architecture Reference Manual describes a low-power multicore parallel computing fabric that connects many cores in a low-latency mesh network-on-chip (NoC).

The Xilinx Zynq-7000 Extensible Processing Platform (EPP) Reference Manual describes technical details about a family of FPGA logic devices with embedded Arm Cortex-A9 MPCores.

The Multicore Association's Multicore Communications API (MCAPI) Specification supports interaction between multiple processing cores, as does their Multicore Resource API (MRAPI) Specification.

Plurality's HyperCore Architecture White Paper summarizes and illustrates their shared-memory multicore architecture for parallel applications.

The Sony, Toshiba, IBM (STI) Cell Broadband Engine Programming Handbook is a 900-page book describing programming for nine heterogeneous cores. The chip is used in the Sony PlayStation 3 game platform.

Cadence Tensilica's Vectra DSP Engine Data Sheet describes a vector-instruction DSP pipeline architecture for their multi-configurable intellectual-property (IP) cores.

The PMC-Sierra RM9000x2 Integrated Multiprocessor User Manual describes a chip with multiple MIPS processor cores and supporting logic for network routing.

NVIDIA's PortalPlayer PP5001 Superintegration System-on-Chip Controller Databook describes the microarchitecture and programming of a multicore SoC for audio media.

Qualcomm Ubicom's IP2022 Internet Processor Data Sheet describes a multicore Internet processor architecture that is reconfigurable over the Internet.

RISC Processors

Arm's Architecture Reference Manual describes the ARMv8 RISC microprocessor architecture.

Arm's Architecture Reference Manual Supplement describes the Memory System Resource Partitioning and Monitoring (MPAM) extension for the Arm microprocessor architecture.

Adapteva's Epiphany Architecture Reference Manual describes its RISC instruction set, pipeline, and onchip network for their multicore parallel-computing fabric.

The Sony, Toshiba, IBM (STI) Cell Broadband Engine Programming Handbook describes programming for nine heterogeneous RISC cores. See PowerPC for more RISC processors.

The Xilinx PPC405 User Manual for the Virtex-II Pro Platform FPGA Developer’s Kit describes a PowerPC RISC processor core embedded in FPGA logic. See PowerPC for more RISC processors.

Cadence Tensilica's Xtensa Instruction Set Architecture (ISA) Reference Manual describes their MIPS RISC instructions and programming model.

The Imagination MIPS Corporation Brochure gives an overview of the company's history, products, and markets.

The PMC-Sierra RM9000x2 Integrated Multiprocessor User Manual describes a MIPS multiprocessor system-on-chip (SoC) for control- and data-plane network routing.

NEC's VR5400 MIPS Processor Product Brief describes the processors and system controllers in this family of MIPS chips.

Fujitsu's SPARClite MB86937 Lumiere RISC Imaging Accelerator User's Manual describes an SPARC-based embedded processor with graphics acceleration implemented as a systems-on-chip (SOC). See SPARC for more RISC processors.

Fujitsu's SPARClite Microprocessor User's Guide describes this RISC processor's microarchitecture and instructions. See SPARC for more RISC processors.

IDT's IDT79R5000 RISC Microprocessor Reference Manual describes the MIPS-architecture instruction set for this processor. See MIPS for more RISC processors.

AMD's Am29050 Microprocessor User's Manual describes this RISC processor's microarchitecture and instruction-set architecture.

x86 Processors

The AMD x86-64 Architecture Programmers Manual, describes their 64-bit x86 application- and system-programming instruction set. See AMD for more of our x86 documents.

AMD's K9 Message Engine Architecture, describes a hardware accelerator design for high-speed message exchange.

NexGen's Nx586 Processor Databook describes their implementation of the x86 architecture. We also wrote their Nx686/Nx687 Processor Databook.

This diagram summarizes the fields and functions of Intel's Pentium Pro x86 internal control registers, with a text summary of each field.

UMC's U5S 486 Green CPU Data Book describes the instruction set and signal interface of this x86 processor.

The AMD-K5™ Technical Reference Manual describes the hardware and software architecture of this processor. It contains examples of cache coherency and interrupts.

Intel's 486 Microprocessor Family Programmer's Reference Manual describes the complete 486 instruction set and programming model. See Intel for more of our x86 documents.

PowerPC Processors

IBM's PowerEN PCIe Card User Manual describes a card that uses an IBM PowerEN processor to monitor high-volume packet traffic in edge-of-network routers.

Sony's Guide to Cell/B.E. Programming Documentation for the Sony PlayStation 3, in which a PowerPC core manages eight SIMD cores. We also wrote the Cell Broadband Engine Programming Handbook.

The Sony, Toshiba, IBM (STI) Cell Broadband Engine Programming Handbook describes parallel programming for this Cell Processor chip, which is used in the Sony PlayStation 3 game platform.

The Xilinx PPC405 User Manual for the Virtex-II Pro Platform FPGA Developer’s Kit describes a PowerPC processor core embedded in field-programmable gate array (FPGA) logic.

IBM's PowerPC Tools catalog describes the system-software and hardware tools that support system development based on PowerPC microprocessors.

IBM's PowerPC Compiler Writer's Guide describes how to write a compiler for microprocessors that run the PowerPC instruction set architecture (ISA).

We created this diagram for PowerPC microprocessors to show how addresses generated by programs (called "effective addresses") are translated into addresses that access memory (called "real addresses").

Arm Processors

Arm's Architecture Reference Manual describes the ARMv8 multicore microprocessor architecture.

Arm's Architecture Reference Manual Supplement describes the Memory System Resource Partitioning and Monitoring (MPAM) extension for the Arm microprocessor architecture.

AppliedMicro's X-Gene 3 64-bit ARM Server SoC User's Manual describes an Arm multicore SoC for data-center applications. We also did their:
X-Gene 2 User Manual and
X-Gene 1 User Manual

Spreadtrum's Javelin Microarchitecture Specification describes the RTL-code functions and interfaces for an Arm multicore processor.

The Xilinx Zynq-7000 Extensible Processing Platform (EPP) Reference Manual describes technical details about a family of FPGA logic devices with embedded Arm Cortex-A9 MPCores.

picoTurbo's pT-120 Hardware Core Data Sheet describes technical details about this Arm-compatible processor core that is designed for systems-on-chips (SoCs).

NeoMagic's LinkUp L7205 Internet System Processor (DSP Enhanced) Databook describes the instructions and microarchitecture of their Arm-based, DSP-enhanced Internet processor.

MIPS Processors

Cadence Tensilica's Xtensa Instruction Set Architecture (ISA) Reference Manual describes their MIPS instructions and programming model. We also wrote their instruction-extension manuals.

The PMC-Sierra RM9000x2 Integrated Multiprocessor User Manual describes a MIPS multiprocessor system-on-chip (SoC) for control- and data-plane network routing.

The Imagination MIPS Corporation Brochure gives an overview of the company's history, products, and markets.

NEC's VR5464 MIPS Processor User's Manual describes the instruction-set architecture (ISA) and hardware of a 64-bit MIPS microprocessor.

NEC's VRC5074 MIPS System Controller Data Sheet describes the interfaces and configuration of a MIPS controller.

IDT's IDT79R5000 RISC Microprocessor Reference Manual describes the MIPS-architecture instruction set for this processor.

SPARC Processors

Fujitsu's SPARClite MB86831 Data Sheet describes the signal interface and register set of a family of SPARClite embedded processors.

Fujitsu's SPARClite MB8683x User's Guide describes the programming of a family of SPARClite embedded processors.

Fujitsu's SPARClite User's Guide describes this embedded processor's hardware microarchitecture and instruction-set architecture.

System on Chip (SoC), ASIC, and ASSP

The Xilinx UltraFast Design Methodology Guide for All Programmable SoCs describes a methodology for designing programmable systems quickly, effectively, and reliably.

The Xilinx Zynq-7000 Extensible Processing Platform (EPP) Reference Manual describes technical details about a family of FPGA logic devices with embedded Arm Cortex-A9 MPCores.

The Synopsys Systems-on-Chip for High-Speed Communication Systems white paper describes design issues and solutions for ASIC-based SoCs used in broadband communications.

NVIDIA's PortalPlayer PP5001 Superintegration System-on-Chip Controller Databook describes the microarchitecture and programming of an SoC core for audio appliances.

Fujitsu's SPARClite MB86937 Lumiere RISC Imaging Accelerator User's Manual describes an embedded processor with graphics acceleration implemented as an SoC.

The PMC-Sierra RM9000x2 Integrated Multiprocessor User Manual describes a MIPS-architecture multiprocessor SoC for control- and data-plane network routing.

Memory

Cisco Memoir's 2R1W Memory IP Core for SRAM Datasheet describes a memory IP core that wraps around standard one-port SRAM1D macros to support two-port functionality.

The Sony, Toshiba, IBM (STI) Cell Broadband Engine Programming Handbook contains a chapter on memory organization that covers system and application memory for all nine processors on the chip.

We created this diagram for PowerPC microprocessors to show how addresses generated by programs (called "effective addresses") are translated into addresses that access memory (called "real addresses").

AMD's Am29000 Microprocessor Memory Design Handbook provides detailed examples of memory design for the Am29000 RISC microprocessors.

Renesas Hitachi's Synchronous Static RAM Application Note describes and illustrates examples of SSRAM cache memory design.

Zilog's Z80 DMA Technical Manual describes the DMA's signal interface and programming for memory-to-memory transfers.

Peripherals and I/O

The Mobile Industry Processor Interface (MIPI) Alliance's Camera Serial Interface 3 (CSI-3) specifies a serial interface for integration of camera subsystems and bridge devices with a host processor.

The Mobile Industry Processor Interface (MIPI) Alliance's Specification for Display Serial Interface specifies a graphic Display Serial Interface (DSI) used in cell phones and mobile devices.

Qualcomm Ubicom's SX Virtual Peripheral Methodology and Modules User's Manual describes the use of a set of virtual peripheral modules.

The Microchip Standard Microsystems Corporation (SMSC) LPC47N359 Mobile Embedded System Controller Specification describes a mobile embedded system controller with LPC, ACPI, SPI, SFI, UART, PS/2, Flash, and debug interfaces.

NeoMagic's LinkUp L1121 CompactFlash/PC Card Interface Chip Data Sheet describes their their L1121 Flash card peripheral-interface chip.

NEC's VRC5074 MIPS System Controller Data Sheet describes the peripheral interfaces and configuration of a MIPS controller.

Cirrus Logic's Voyager CL-PS7000 Apple Newton PCA Chip Set Engineering Specification specifies a peripheral-controller chip used in the Apple Newton mobile device.

Zilog's Z80 DMA and SIO Data Sheets describes the Z80 peripherals and the programming of their interfaces and drivers.

Field-Programmable Gate Arrays (FPGAs)

The Xilinx UltraFast Design Methodology Guide for All Programmable SoCs describes a methodology for designing programmable systems quickly, effectively, and reliably.

The Xilinx Zynq-7000 Extensible Processing Platform (EPP) Reference Manual describes technical details about a family of FPGA logic devices with embedded Arm Cortex-A9 MPCores.

Altera's Interlaken Megacore Function Users Guide describes their serial communication protocol for chip-to-chip packet transfers.

Synopsys' FPGA-Based Prototyping Methodology Manual describes a systematic method for prototyping chips and boards using FPGA logic.

The ElementCXI Elemental Computing Array Principles describes a programmable-logic system and the CAD tools used to create it.

The Xilinx PPC405 User Manual for the Virtex-II Pro Platform FPGA Developer’s Kit describes how to configure FPGA logic that surrounds an embedded PowerPC processor core.

Xilinx's Logic Cell Array (LCA) User's Manual describes the hardware for a product line of reconfigurable FPGA logic.

Mixed Signal, RF, and GPS

The Near Field Communication (NFC) Forum's Test Cases for Digital Protocol specifies test methods used for near-field devices, which are based on radio-frequency identification (RFID) standards.

The MIPI Alliance's Specification for RF Front-End (RFFE) Control Interface defines a common method for controlling RF front-end devices.

The MIPI Alliance's Specification for DigRF defines the interface between Baseband ICs (BBICs) and Radio Frequency ICs (RFICs) in a single terminal.

SiRF's GSD4t GPS Hardware and Software Databook describes a mixed-signal global positioning system (GPS) chip that is designed for use in cell phones and mobile navigation devices.

Sinett's SN5024 Unified Wireless and Wired Edge-Switch Datasheet describes a wireless and wired network edge switch.

Analog Devices' Dust Network's SDK Template describes how to write user guides for their wireless ZigBee Green Power (ZGP) core and board-support package (BSP).

Ditrans' DT3824 JAZZ CDMA/AMPS Tri-Mode, Dual-Band Receiver Data Sheet describes a mixed-signal chip used in dual-band cell phones.

Wheels of Zeus (WoZ) Global Positioning System (GPS) Preliminary Engineering Specification Proposal describes the hardware and software parameters for a GPS microchip.

Tchip's IP1012 Global Positioning System (GPS) Receiver Baseband Data Sheet describes a baseband (non-modulated) receiver chip used in GPS devices.

Digital Signal Processors (DSPs)

NeoMagic's LinkUp L7205 Internet System Processor (DSP Enhanced) Databook describes the instructions and microarchitecture of their Arm-based, DSP-enhanced Internet processor.

Cadence Tensilica's Vectra DSP Engine Data Sheet describes a vector-instruction DSP pipeline architecture for their configurable intellectual-property (IP) cores.

Conexant's Countach-40 DSP Architecture Reference Manual describes the processor's instruction set and programming model.

Hitachi's (now Renesas') SH-DSP 7410 Hardware Manual describes the microarchitecture of an SH-DSP processor. We also wrote their SH-DSP Programming Manual.

Analog Devices' ADSP-2100 Family User's Manual describes the hardware architecture and instruction-set architecture of this family of DSP chips.

Cell Phones and Mobile Devices

The Mobile Industry Processor Interface (MIPI) Alliance's Specification for Unified Protocol (UniPro) v2.0 defines a layered protocol for interconnecting devices and components within mobile systems.

The Mobile Industry Processor Interface (MIPI) Alliance's Camera Serial Interface 3 (CSI-3) specifies a serial interface for integration of camera subsystems and bridge devices with a host processor.

The MIPI Alliance's Specification for Unified Protocol (UniPro) SDL State Machines defines Specification and Description Language (SDL) state machines for cell phones and mobile devices.

The MIPI Alliance's Specification for Serial Low-power Inter-chip Media Bus (SLIMbus) defines a two-wire multi-drop interface for digital audio and control devices.

The MIPI Alliance's Specification for RF Front-End (RFFE) Control Interface defines a common method for controlling RF front-end devices.

The Near Field Communication (NFC) Forum's Test Cases for Digital Protocol, one of several NFC standards that we have edited.

SiRF's GSD4t GPS Hardware and Software Databook describes a mixed-signal global positioning system (GPS) chip that is designed for use in cell phones and mobile navigation devices.

Ditrans' DT3824 JAZZ CDMA/AMPS Tri-Mode, Dual-Band Receiver Data Sheet describes a mixed-signal chip used in dual-band cell phones.

Wheels of Zeus (WoZ) Global Positioning System (GPS) Preliminary Engineering Specification Proposal describes the hardware and software parameters for a GPS microchip.

Tchip's IP1012 Global Positioning System (GPS) Receiver Baseband Data Sheet describes a baseband (non-modulated) receiver chip used in GPS devices.

Computer Systems

Barco's PDS Digital and Analog Video Switcher User's Guide describes its digital-signage processor, video scaler, scan converter, switcher, and transcoder.

Nanosphere's Verigene Molecular Diagnostics System User's Manual describes a molecular diagnostics workstation used in medical and molecular biology research and clinical applications.

Siemen's Cluster Framework (SCF) Overview describes a server clustering system that supports enterprise web sites, storage networks, and data bases with load-balancing and firewall security.

IBM's Metaphor Database Server 200 Operations Manual describes a network-based server supporting SQL relational databases.

Convergent Technologies' IWS Workstation Hardware Manual describes an OEM workstation for computer-system manufacturers.

Saudi Consolidated Electric's SICON Jubail System Engineer's Manual describes a system control and data acquisition (SCADA) system for airports and electric-power systems in Saudi Arabia.

Apple's Lisa Owner's Guide describes how to install and maintain all of the user hardware and software features of the Lisa computer system.

GRiD Systems' Getting Started with the GRiD Compass describes the user software and hardware features of a mobile laptop computer.

Development Tools

The Xilinx UltraFast Design Methodology Guide for All Programmable SoCs describes a work-flow methodology for designing programmable systems quickly, effectively, and reliably.

The NetSpeed NocStudio User Manual describes design-flow methodology for the specification, design, evaluation, and generation of IP files including RTL, testbench, C++ models, synthesis scripts, and IP documentation.

The Mobile Industry Processor Interface (MIPI) Alliance's Specification for Processor Interface Emulation specifies the architecture for an emulator of the processor-interface used in cell phones and mobile devices.

ElementCXI's Alchemy Design Tools ECA-64 Tutorial describes the CAD tools used to create its reconfigurable logic.

Hitachi's D9000 Development System Hardware User Manual describes how to develop hardware and software in the Windows CE operating-system environment on their SH family of processors.

Cadence Tensilica's Xtensa Software Development Toolkit User's Guide describes their GNU tool chain that supports software development.

AMD's SimNow Simulator 3.0 User Manual describes a software simulator that can accurately represent and debug a complete software system (applications, drivers, and OS).

IBM's PowerPC Tools catalog describes the system-software and hardware tools that support system development based on PowerPC microprocessors.

The Xilinx Advanced CAD Technology (XACT) User's Manual describes the computer-aided design (CAD) tools used for implementing their Logic Cell Array (LCA) FPGAs.

Installation and Maintenance

IBM's PowerEN PCIe Card User Manual describes the installation and operation of this single-board computer for edge-of-network network applications.

Zircon's Installation Guide for UNIX Platforms is for a middleware API that maps mission-critical applications to a pool of heterogeneous hardware and OS platforms.

The Sony, Toshiba, IBM (STI) Cell Broadband Engine Hardware Initialization Guide describes how to boot and test this multicore processor.

Applied Materials' Varian 3190 Cassette-to-Cassette Sputtering System Maintenance Manual describes the maintenance procedures for this electro-mechanical-chemical manufacturing machine.

Applied Materials' Varian MDP-1000 Disk Sputtering System Maintenance Manual describes the maintenance procedures for this disk sputtering system.

Electric Energy

This Electric Reliability Council of Texas (ERCOT) Customer Move-Out State Transitions diagram defines building move-out scenarios based on Karnaugh maps that Warthman Associates devised.

Electric Power Software's Load-Management Strategy Testing Model (LMSTM) Reference Guide describes a modeling systems for electric-power energy management.

The Electric Power Research Institute (EPRI) User's Guide to the Over/Under Capacity Planning Model describes simulation and modeling systems for electric-power capacity planning.

The Energy Management Associates (EMA) PROMOD III Production Costing Model User's Manual describes methods for estimating the cost of electric-power production.

Saudi Consolidated Electric's SICON Jubail System Engineer's Manual describes the engineering maintenance of a SCADA system for airports and electric-power systems in Saudi Arabia.

Artificial Intelligence, Neural Networks, and Pattern Recognition

Wave Computing's Teal Architecture Specification describes a chip architecture for machine-learning dataflow computers, such as those that support TensorFlow.

Intel/Nestor's Ni1000 Recognition Accelerator User's Guide describes the Ni1000 chip's real-time classification of patterns using artificial neural-network radial basis function (RBF) algorithms.

Intel/Nestor's Ni1000 Recognition Accelerator Technical Specification describes a classification engine for pattern recognition.

Intel's 80170NX Neural Network Solutions Brochure summarizes their electrically trainable analog neural network chip.

Intel's 80170NX Electrically Trainable Neural Network Data Sheet describes an electrically trainable analog neural network chip.

Warthman Associates developed the hardware for two audio synthesizers, based on Intel neural-network chips. One box had its world premier concert at the Paris Opera House with the Merce Cunningham Dance Company.

Warthman Associates wrote this article for Dr. Dobbs Magazine that describes our neural-network audio synthesizers.

Industrial and Automotive

AMS' AS5048 Magnetic Rotary Encoder Datasheet describes a family of magnetic rotary encoder chips.

Trinamic's TMC262 Datasheet describes a semiconductor and driver for stepper motors used in automotive and industrial applications.

Trinamic's Trinamic TMC262 Evaluation Manual describes a a board with TMC262 chip, power MOSFETs, and a microcontroller. It interfaces to a PC for visualization and control of parameters.

Infineon's Hall-Effect Integrated Switches and Latches Application Note describes a magnetic-field-sensing microchip used in industrial and automotive applications.

WaferScale Integration's PAC1000 Microcontroller Data Sheet describes the signal interface and programming of a microcontroller chip.

Signetic's 8X305 Bipolar Microcontroller User's Manual describes the signal interface and programming of the industrial microcontroller.

Semiconductor Processing

OAI's Model 5000 and 8000 Auto-Load Mask Alignment System User Manual describes the operation of two mask aligners.

ASML's DSM Design Reference describes one of their software tools for semiconductor mask lithography.

Applied Materials' Varian 3190 Cassette-to-Cassette Sputtering System Operation Manual describes an electro-mechanical-chemical manufacturing machine for semiconductor chips.

Applied Materials' Varian MDP-1000 Disk Sputtering System Operator's Manual describes how to operate this disk sputtering system.

GlaxoSmithKline's Branson/IPC Sigma 80 Technical Brochure gives a graphic overview of a plasma etching system used to make integrated circuits.

GlaxoSmithKline's SmithKline Beecham Branson/IPC 6120 Plasma Etching System User's Manual describes describes how this plasma etching system is used to make integrated circuits.

Testing

SÜSS MicroTec's Micron Force Instruments (MFI) Real-Time Prober User's Guide describes a real-time IC wafer prober.

OAI's TriSOL 300mm Solar Simulator User Manual describes the operation of this solar simulator for 300mm wafers.

The Near Field Communication (NFC) Forum's Test Cases for Digital Protocol specifies the test methods to be used for near-field devices.

Nanosphere's Verigene Molecular Diagnostics System User's Manual describes a molecular diagnostics workstation used in medical and molecular biology research and clinical testing.

Fluke's 9100A/9105A Automated Operations Manual describes an automatic testing system for semiconductor circuit boards.

KLA-Tencor's Flatgage Wafer and Photomask Flatness Tester Data Sheet is a specification and quick guide for this wafer and photomask flatness tester.

KLA-Tencor's Alpha-Step 200 Data Sheet describes and illustrates the electromechanical properties and operation of this semiconductor test instrument.