Microprocessor Address Translation

This block diagram summarizes how Effective Addresses, generated by programs running on a 32-bit IBM PowerPC™ microprocessor, are translated into Real Addresses that access locations in memory. The address translation shown here applies to memory accesses that hit in (i.e., locate a prior address-translation in) the processor's on-chip translation lookaside buffer (TLB).

The diagram is designed for an audience of system-software programmers.


PowerPC effective addresses consist of a segment register (SR) field, which serves as a segment index, and the page and byte fields, which serve as a segment offset. In this implementation of a PowerPC processor, the SR field selects one of 16 segment registers, and the least-significant (low-order) seven bits of the page field select one of 127 sets in both ways of a two-way TLB. Each entry in the TLB contains, among other information, a VSID field (virtual segment ID), an API+3 field (abbreviated page index + 3 contiguous low-order bits), and an RPN field (real page number).

To translate an effective address, the memory management unit performs two simultaneous comparisons: (a) the VSID in the segment register is compared with the same fields of both TLB ways, and (b) the API+3 field in the effective address is compared with the same fields of both TLB ways. The RPN of the successfully compared TLB way is then used as the high 20 bits of the real address, and the low 12 bits are copied from the effective address.


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