Microprocessor Cache-Coherency Snooping
The term "snooping" commonly refers to at least three
different actions, only two of which are supported by the AMD-K5
and Pentium processors:
The table below shows the conditions under which snooping occurs in the AMD-K5 processor and the resources that are snooped. All such snooping is done in the processor's physical tags, in parallel with the processor's own accesses to the linear tags. Thus, there is no execution-performance penalty for snooping.
|Origin of Snoop||Type of Access||Snooping Action|
|Instruction Cache||Prefetch Buffer||Line-Fill Buffer||Data Cache||Store Buffer||Writeback Buffers|
|Internal||Instruction Cache||Read Miss||n.a.||n.a.||n.a.||yes2||yes2||yes2|
1. The processor's response to a snoop hit depends on the state of the INV input signal and the state of the cache line. If INV is negated, the line remains in or transitions to the shared state. If INV is asserted, the line is written back, if modified in the data cache, and then invalidated.
2. If the snoop hits a line in the data cache, store buffer or writeback buffer, the line is written back (if modified) and invalidated. Then, the instruction-cache read is performed again. If the line is modified, a copy of the writeback data is passed directly to the instruction cache, thus avoiding a line-fill bus cycle after the writeback bus cycle.
3. If the snoop hits a line in the instruction cache, prefetch buffer, or line-fill buffer, the line stays valid and the data-cache read is performed again, but as a single, non-cacheable read.
4. If the snoop hits a line in the instruction cache, prefetch buffer, or line-fill buffer, the line is invalidated and the data-cache write is performed.
n.a. = not applicable
In systems with multiple caching masters, external logic maintains cache coherency by driving inquire cycles to the processor. System logic initiates inquire cycles by asserting AHOLD, BOFF#, or HOLD to obtain control of the address bus, and then driving EADS#, INV and an inquire address. Such bus cycles cause the processor to compare the physical tags for both its instruction and data caches with the inquire address. If the compare hits a shared or exclusive line in the data cache or a valid line in the instruction cache, the processor asserts HIT#. If the compare hits a modified line in the data cache, the processor asserts HITM#.
The resulting state of a cache line that is hit depends on the state of the INV signal at the time of the inquire cycle. If INV is negated, the line remains in or transitions to the shared (or valid) state. If INV is asserted, the line is written back, if modified in the data cache, and then invalidated.
The processor automatically snoops its instruction
cache during read or write misses to its data cache, and it snoops
its data cache during read misses to its instruction cache. It
does this to detect the presence of self-modifying code. If an
internal snoop hits its target, the processor does the following:
The AMD-K5 processor, like the 486 processor but unlike the Pentium processor, requires a jump (near or far) after a self-modifying write to clear the prefetch buffer. However, both the AMD-K5 and the Pentium processors require a serializing instruction after self-modifying code whose physical address is aliased to multiple linear addresses.