Forrest Warthman is the founder of Warthman Associates, and he continues to lead writing projects as a principal writer, editor, and project manager. He has personally written many of the documents listed on the projects page.
Forrest gave a presentation on Cities and Computers: Their Architecture at University of California, Berkeley, and at Stanford University. The presentation describes computer functions that work like city functions.
In addition to writing, Forrest has designed and led the development of six hardware and software prototypes, including a prototype for a flat-panel handwriting and drawing device, a cost-accounting application marketed in cooperation with Microsoft, a file-conversion application, two audio synthesizers based on Intel neural-network chips, and several Java animations.
Forrest received an M.A. in City Planning and an M.A. in Architecture from the University of California at Berkeley. His city-planning thesis, on urban telecommunication networks, was written under the chairman of the EE/CS Department. His architecture thesis, on transportation networks, was written under the chairman of the Transportation Engineering Department. He received a B.S. in Design from the University of Michigan.
John Goetz has had a 23-year career at IBM as a microprocessor and computer-system architect, product marketing manager, verification-tool developer, and logic designer. He has written technical manuals and engineering specifications throughout his career, including documents about the Cell Broadband Engine (CBE), PowerPC, x86, and MIPS processor architectures, network processors, and reconfigurable logic. At Warthman Associates, John has written technical documents for AMD, PMC-Sierra, and Xilinx about the x86, PowerPC, and MIPS processor architectures, and for Infineon about industrial semiconductors.
Prior to Warthman Associates, John was at IBM for 23 years, most recently as a senior engineer in IBM's Global Engineering Solutions (GES) architecture group, where he architected embedded imaging solutions based on the Cell multiprocessor and ASICs for the aerospace, defense and health care industries, including CT, PET, MR, and ultrasound technologies. Before that, he taught high-school mathematics and wrote standard specifications for the RapidIO Trade Association. He was a senior engineer and marketing manager for IBM's Network Processor Business Line, where he defined new PowerPC-based products and positioned existing products for network applications. Before that he was a senior processor architect working on product strategy of system-on-chip (SoC) PowerPC products and x86 business relationships. He architected and led the verification of an operating mode for the PowerPC 615 processor that executed multiple instruction sets, and he served as the in-house consultant to IBM design and verification teams on all issues related to PowerPC and x86 instruction-set architectures. He was the principal editor of the engineering specification for the PowerPC 615 processor. Prior to that he managed the department responsible for IBM’s x86 processor architectures and verification. He began his career at IBM in electronic design automation (EDA), responsible for developing simulation and logic-synthesis tools.
He has five patents in areas including microprocessor cache design, multiple-instruction-set support, and logic-network optimization.
John received his B. S. in Electrical Engineering from University of Notre Dame, followed by masters coursework in microprocessor architecture and operations research at the University of Vermont.
Rob Johnson is an engineer and technical writer specializing in consumer-electronic product development. He has written many technical and developer documents for graphics processors, I/O chipsets, wireless network devices, process development, and software-quality engineering. He has also edited new-technology specifications for industry alliances supported by the IEEE Industry Standards and Technology Organization (ISTO), including the Mobile Industry Processor Interface (MIPI) alliance and the Linux Mobile (LiMo) foundation.
Before joining Warthman Associates, Rob worked at Intel where he developed software for new chipsets including the Intel®810 graphics and early Centrino™ wireless products. He architected and coded the video-capture drivers and interrupt subsystems for the graphics chipsets as well as bringing up the hardware. He also authored protocol-analyses and architecture proposals for Intel’s integrated wireless products. He was directly responsible for developing and writing programmer’s reference manuals for multiple chipsets, training materials for software-process improvement and innumerable reports, proposals, and other engineering documents, as well as leading product-development teams for Linux drivers. At GTG Productions, Rob created software for enhanced CDs that included disc and audio control and installers for such artists as David Bowie, Brian Eno, and Todd Rundgren. He also developed programmable high-performance ignition systems for Yamaha jetskis and an audio mixer plug-in for Macromedia Director®. Prior to GTG Productions, Rob developed toys for Hasbro®, Lionel®, and Chase Toys, including a GI Joe playset and the TrainMaster® Command Control system which was debuted at the Asilomar Microcomputer Conference. Previously, he was chief engineer for C & K Systems’ System238™ Residential/Commercial Security Panel, developing the hardware, software, and communication architectures as well as the product requirements, user’s guide, and product datasheet.
Rob attended Virginia Tech and Hayward State Universities before receiving his B.S. in Electrical Engineering from the University of Nevada, Reno. He has also taken coursework in program management, Linux driver development, software-development life cycles, patent development and product branding and trademarking. Rob is a cycling enthusiast, having ridden all over the world including the 2003 Tour de France route.
Martin Morf is a content consultant to Warthman Associates' writers. He is an expert in the theory of information, control, estimation, and computer architecture. He is active in research on smart photonic networks, parallel and adaptive computing, specialized coprocessors (fluid-flow, communications, real-time control, and DSP), micro-MRI informatics, brain imaging, electro-optical and quantum devices, sub-nanosecond arithmetic processing, and information-preserving transformations. He has participated in a wide variety of research projects, most recently in projects that bring together the disciplines of biology, information technology, microelectronics, and physics.
He has been Visiting Professor of Electrical Engineering at Stanford University, Codirector of the Stanford Computer Architecture and Arithmetic Group, Professor of Computer Science at ETH Zurich, Professor of Electrical Engineering and Computer Science at Yale University, and Visiting Professor at several institutions including NASA/Ames Research Center, Stanford University's Center for Integrated Systems, Xerox PARC, IBM T.J. Watson Research Center, and ETH Zurich's Institute for Control, Institute for Biomedical Engineering, and Institute for Mathematics. He has also conducted research projects for Canon Research America, Xerox PARC, RCA, and Chevron Research. Early in his career, he served in the Swiss Army Signal Corps.
He has authored or coauthored over 250 publications, including recent publications on reconfigurable and adaptive computing, photonic modulation and routing, computing-system optimization, estimation theory, nanotechnology architectures, and speech modeling.
Martin received his Federal Diploma in Electrical Engineering at ETH Zurich, and his M.S. and Ph.D. in Electrical Engineering at Stanford University. He also received an honorary M.A. from Yale University.